Weight-based FPGA placement algorithm with wire effect considered was presented. The algorithm can support modern FPGA architecture with different kinds of blocks, such as carry chain, DSP, BRAM, etc. Different weight factors are introduced to different placement blocks with wire effect considered. In this way, the placement cost and time could be optimized to maximize extent. The experiment results, targeting on FDP5 chip with ten million system gates, which is developed by Fudan University independently, show that the proposed algorithm could support modern FPGA architecture perfectly. Furthermore, compared with Xilinx's CAD tool ISE, on average, the proposed placer could achieve 95% placement quality at the cost of a 3% increase in run time.
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