Design and FPGA-based multi-channel, low phase-jitter ADPLL for audio data converter

摘要

This paper, focus on design, analysis and simulation of an All Digital Phase Locked Loop (ADPLL) for high-resolution audio data converters applications with a low jitter effect. The design procedure is based on the analogy between a Discrete Voltage Controlled Oscillator (DVCO) and a Direct Digital Frequency Synthesis (DDFS). To verify the analysis experimentally, an FPGA-based ADPLL implementation using model-based design is described. Its effectiveness is validated by a reducing hardware requirements and increasing performance.