HSSL specification high-level synthesis

摘要

Hardware description languages (HDLs) can describe a digital system at several layers of abstraction, typically starting at register transfer level (RTL). Due to the instant growth in the modern designs complexity, there is an urgent need to specify the system at the more abstract layer, the system layer. The paper deals with the problem of transformation of formal behavioral specification in HSSL (Hardware-Software Specification Language) into the VHDL model. The HSSL supports system-level behavioral specification of a digital system and its refinement to the RTL behavioral specification. At this point the high-level synthesis should be used to convert the specification into an HDL to allow for the lower-level design steps to be performed by the commonly used CAD (Computer Aided Design) tools. As VHDL is the most common HDL, it has been chosen for this purpose. The goal of the presented research is to design and implement methods and tools that would allow for the automation of the high-level synthesis. The proposed transformation is based on a Petri net formal model. The transformation system has been implemented in C#.