This paper presents a novel approach for cryptology-specific instructions generation on a reconfigurable architecture which is named ASRA. The ASRA tightly integrates a customized reconfigurable core with a very-long instruction word basic core. Both cores in ASRA can work in parallel. The methodology for cryptology-specific instruction generation can directly deploy algebraic operations as primitives for ASRA's custom function units (CFUs), and is able to eliminate a large portion of design space exploration difficulty from conventional data-flow graph methods. Cryptology-specific instructions for block cipher and hash algorithms which are kernel data processing tasks in security applications are exploited. Then an accelerator prototype of the ASRA is built on a Xilinx Kintex-7 FPGA chip. Experiment results show that our work achieves a high performance improvement and a good flexibility.
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