The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed to enhance the ability of parallel computation. Iterative loops are the main body of applications mapping on the CGRAs. The loop management critically affects the efficient mapping of applications. Limited by special hardware controllers, the loop management brings great difficulties to flexible and efficient use of CGRAs. In this paper, we propose a novel loop adaptive hardware design for CGRAs. With innovative Shared Register Files (SRFs) and extended operations for Reconfigurable Cells (RCs), our loop adaptive design can be applied to a wide range of CGRAs. SRFs are designed for data communication in a System-on-Chip. And extended reconfigurable operations are designed for the adaptive loop prologues and epilogues management. Experimental results demonstrate that when compared with conventional processors, our work achieves a significant speedup improvement in total cycle number and IPC (Instructions per Cycle). In addition, proposed design not only decreases logic area but also greatly reduces complexity of hardware implementation.
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