Digital Control of PD-SPWM Algorithm for Three-Level Inverter Using FPGA Device

摘要

In this paper, a phase disposition sinusoidal pulse width modulation (PD-SPWM) is used to control three-phase 3-level NPC inverter. The gate signals are generated with FPGA-Spartan 3E Board. The PD-SPWM algorithm is described in VHDL and simulated using ModelSim. The simulation results given by Matlab/Simulink are compared to the experimental results using three-phase 3-level IGBT inverter.