A 9.9G-10.8Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

摘要

A 9.9-10.8Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5μm SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2mUlrms jitter generation and 0.4SUlpp jitter tolerance in a 4-80MHz range. Power dissipation is 1.45W from a 3.3V supply.