A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

摘要

As serial links push to higher data rates, more sophisticated equalization schemes are required to counter the effects of ISL DFE is favored to cancel post-cursor ISI since it does not amplify noise or reduce received signal strength. Furthermore, it is necessary in today's backplanes for the DFE to automatically adapt to the characteristics of the channel [1]. This paper describes the architecture and circuits to address three important concerns of such DFEs: closing timing to cancel the ISI from immediately preceding bits, ensuring the proper convergence of the adaptation algorithm, and providing in-situ diagnostics capabilities.