A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS

摘要

Filters are key building blocks in wireless communication and analog signal processing. Typically, Gm-C and active-RC topologies are being used for this purpose. However, reduced supply voltage and lower transistor output impedance make it difficult to implement high-gain wide-bandwidth opamps in a power-efficient manner. Moreover, portable wireless communication devices demand nowadays ever decreasing power consumption, and more tunability/reprogrammability. A discrete-time (DT) analog signal processing approach appears to answer these requirements.