To investigating high throughput pattern matching of regular expressions, This paper present a novel NFA-based architecture. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic module to construct NFA which easily were reused in a FPGA or ASIC. Our approach is able to process many symbols per one clock cycle, and to run at high frequency. Due to FPGA constraints, the throughput of our approach achieved 512Gbps. The latency of our approach is lower than 2ns.
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