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A Novel Power Management for CMP Systems in Data-Intensive Environment

机译:数据密集型环境中CMP系统的新型电源管理

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The emerging data-intensive applications of today are comprised of non-uniform CPU and I/O intensive workloads, thus imposing a requirement to consider both CPU and I/O effects in the power management strategies. Only scaling down the processor''s frequency based on its busy/idle ratio cannot fully exploit opportunities of saving power. Our experiments show that besides the busy and idle status, each processor may also have I/O wait phases waiting for I/O operations to complete. During this period, the completion time is decided by the I/O subsystem rather than the CPU thus scaling the processor to a lower frequency will not affect the performance but save more power. In addition, the CPU''s reaction to the I/O operations may be significantly affected by several factors, such as I/O type (sync or unsync), instruction/job level parallelism, it cannot be accurately modeled via physics laws like mechanical or chemical systems. In this paper, we propose a novel power management scheme called MAR (modeless, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption under performance constraints. By using richer feedback factors, e.g. the I/O wait, MAR is able to accurately describe the relationships among core frequencies, performance and power consumption. We adopt a modeless control model to reduce the complexity of system modeling. MAR is designed for CMP (Chip Multi Processor) systems by employing multi-input/multi-output (MIMO) theory and per core level DVFS (Dynamic Voltage and Frequency Scaling). Our extensive experiments on a physical test bed demonstrate that, for the SPEC benchmark and data-intensive (TPC-C) benchmark, the efficiency of MAR is 93.6-96.2% accurate to the ideal power saving strategy calculated off-line. Compared with baseline solutions, MAR could save 22.5-32.5% more power while keeping the comparable performance loss of about 1.8-2.9%. In addition, simulation results show the efficiency of our d--esign for various CMP configurations.
机译:当今新兴的数据密集型应用程序由不均匀的CPU和I / O密集型工作负载组成,因此要求在电源管理策略中同时考虑CPU和I / O的影响。仅根据处理器的忙/闲比率降低处理器的频率就无法充分利用节能的机会。我们的实验表明,除了繁忙和空闲状态之外,每个处理器还可能具有I / O等待阶段,以等待I / O操作完成。在此期间,完成时间是由I / O子系统而不是CPU决定的,因此将处理器缩放到较低的频率不会影响性能,但可以节省更多功率。此外,CPU对I / O操作的反应可能会受到多个因素的显着影响,例如I / O类型(同步或不同步),指令/作业级别并行性,无法通过诸如机械或化学系统。在本文中,我们提出了一种在多处理器系统中称为MAR(无模式,自适应,基于规则)的新型电源管理方案,以最大程度地降低性能约束下的CPU功耗。通过使用更丰富的反馈因子,例如在I / O等待时,MAR能够准确描述核心频率,性能和功耗之间的关系。我们采用无模式控制模型来降低系统建模的复杂性。 MAR通过采用多输入/多输出(MIMO)理论和每核级DVFS(动态电压和频率缩放)设计用于CMP(芯片多处理器)系统。我们在物理测试床上进行的大量实验表明,对于SPEC基准和数据密集型(TPC-C)基准,MAR的效率与离线计算的理想节能策略相比,准确率为93.6-96.2%。与基准解决方案相比,MAR可以节省22.5-32.5%的电量,同时保持大约1.8-2.9%的可比性能损失。此外,仿真结果表明,我们的d- -- 设计各种CMP配置。

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