Coprocessing Architecture in System-on-Programmable-Chip for Walk on the Boundary Method to Calculate Capacitance

摘要

Monte Carlo simulation is mainly done in computer clusters, supercomputers or computers coupled with hardware accelerators. These processing methods are sufficiently fast, however, this speed comes at the expense of physical area and power consumption. The current study aims to use System-On-Programmable-Chip (SOPC) to accomplish the same task but using a smaller physical footprint. The SOPC approach takes on a co processing architecture to execute a Monte Carlo algorithm based random walk on boundary (WOB) method to calculate unit cube capacitance. A time extrapolation is performed on the processing rate of the coprocessor to reveal comparable results of a previous work using 1.3 GHz Pentium 4 desktop computer. The performance results can be attributed to a streaming interface which connects the random number generator source and the coprocessor.