Design Approach of a Low-Jitter DDS-Like Frequency Synthesizer Using Mixed-Mode Signal Processing

摘要

In many digital communication systems, the reconfigurable clock is necessary and important, however, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems. In this paper, a low-jitter DDS-like frequency synthesizer without phase accumulator and phase interpolation is proposed, which uses a mixed-mode signal processing that performs the bidirectional integration on single capacitor to directly achieve the clock output with correct time intervals, and it also can avoid the impact on spurious level caused by the capacitance error. Therefore, the proposed DDS-like frequency synthesizer using single capacitor integration can significantly reduce much hardware complexity, and it also obtains a low-jitter and high-precision clock output.