Communication on a segmented bus

摘要

In this study, we discuss communication aspects concerning a segmented bus platform. Placed somewhere midway between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology. The result comes as a parameterized communication scheme for system on chip designers.