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A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC

机译:灵活的500MHz至3.6GHz无线接收器,在7b 21MS / s SAR ADC中嵌入了可配置的DT FIR和IIR滤波器

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摘要

A flexible, digital-dominant wireless receiver in implemented in 65nm CMOS. The receive chain consists of a wide-band LNA, mixers, and baseband amplifiers. A 7b 21MS/s SAR ADC with embedded, configurable DT FIR/IIR filtering rejects aliasing interferers. Interleaving of sampling and SAR in the ADC maximizes conversion rate. The receiver achieves −92 dBm sensitivity, +33dB and +39dB adjacent and alternate channel interferer rejection with 802.15.4 packets, respectively, and −83dBm sensitivity, +41dB, +20MHz interferer rejection with 802.11 packets.
机译:以65nm CMOS实现的灵活的数字主导型无线接收器。接收链由宽带LNA,混频器和基带放大器组成。具有嵌入式,可配置DT FIR / IIR滤波的7b 21MS / s SAR ADC可以消除混叠干扰。 ADC中的采样和SAR交织可最大程度地提高转换速率。接收器分别通过802.15.4数据包实现−92 dBm灵敏度,+ 33dB和+ 39dB邻道和备用信道干扰抑制,而802.11数据包实现−83dBm灵敏度,+ 41dB,+ 20MHz干扰抑制。

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