A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC

摘要

A flexible, digital-dominant wireless receiver in implemented in 65nm CMOS. The receive chain consists of a wide-band LNA, mixers, and baseband amplifiers. A 7b 21MS/s SAR ADC with embedded, configurable DT FIR/IIR filtering rejects aliasing interferers. Interleaving of sampling and SAR in the ADC maximizes conversion rate. The receiver achieves −92 dBm sensitivity, +33dB and +39dB adjacent and alternate channel interferer rejection with 802.15.4 packets, respectively, and −83dBm sensitivity, +41dB, +20MHz interferer rejection with 802.11 packets.