A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications

摘要

We present a 6Gb/s wireline receiver having Frequency Division Multiplexing (FDM) with four frequency sub-channels. Its 6GS/s discrete-time filter consumes less power than a conventional filter which requires the same number of high-speed analog mixers as sub-channels and provides channel filtering of FDM signals that contain four 1.5GSymbol/s data. Improved I/Q-based phase detection using only in-phase amplitude makes possible low-power symbol-rate clock recovery. The FDM receiver fabricated in 90nm CMOS process achieves BER<10⁻¹² over a 25cm low-ε channel, while consuming 250mW from a 1.4V supply.