A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control

摘要

This paper proposes a 10 bit linear interpolation digital-to-analog converter (DAC) with area efficiency and a high resolution for an AMLCD drive. Because this proposed structure implements a 1 bit interpolation circuit with a control block for a loop gain ratio, it shows a wide voltage range of interpolation as well as superior linearity. The proposed circuit is fabricated with Samsung 90nm CMOS 1.5V / 5V technology. The power dissipation is 7uW/channel, and the chip area of the 10 bit piecewise linear DAC is only 91% of the area of a conventional 8 bit resistor DAC. The INL and DNL properties are +0.8LSB/−0.2LSB and +0.23LSB/-0.23LSB, respectively. The maximum interchannel DVO is 10mV without the application of any offset cancellation techniques.