Design of UCL hardware filtering system based on FPGA

摘要

UCL (Uniform Content Locator) which can be used in information management and semantic comprehension has attracted more and more attentions from researchers. In this paper, a hardware system of UCL filtering based on FPGA is proposed. In addition a new type of CAM (Content Addressable Memory) and a hardware platform are designed. In experimental environment, the BIP (Broadcasting Internet Protocol) packets formed by indexing UCL in source side are delivered to user terminals, and the filtering system realizes UCL resolving with FPGA in Ethernet. The results show that the system filtering rate is up to 10Mbit/S and maximum frequency reaches 238MHz.