Presents the hardware implementation of a wavelet image coder. It proposes the architectures to achieve 2-D Discrete Wavelet Transform (DWT) and a fast zerotree image coding (FZIC). The Verilog HDL models for 2-D DWT and FZIC are programmed, and extensive simulation has been carried out to optimize the design. The completed design is synthesized to Altera CPLD.
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