Design of synchronization circuit based on two highspeed multiplexed DACs in satellite transmitter application

摘要

This paper proposes method for synchronization circuit design of two high-speed multiplexed digital-to-analog converters (MUX-DACs) which are used in the shaping filter of high-speed satellite transmitter in order to synchronize I/Q output data. The logic circuit manipulates phase adjustment by detecting phase error and swallowing one of the two DACs' latching clock pulse until the relative phase of the two DACs' latching clock is zero. Through software simulation and hardware verification, the synchronization logic circuit has been proved to be able to efficiently detect and synchronize the data latching clock phase which may be non synchronous for the different initial states of the two clock dividers in I/Q MUX-DACs. This logic circuit has met the requirement for synchronization of I/Q output data in the high-speed shaping filter design. Therefore, the synchronization circuit could be applied to the high-speed satellite transmitter.