A method for measuring the jitter of PLLs

摘要

Jitter of phase-locked loops (PLLs) is an important parameter of clock system in mixed-signal integrated circuits. An improved method is proposed to measure the jitter on PLLs output clock accurately. In this method, the jitter is measured by an analytic signal which is extended from the real signal of PLL output clock, and a double window functions method is used in the frequency analysis to optimize the performance. The results of simulations validate the satisfactory performance of proposed PLL jitter measurement, and the better performance compared with the other methods.