Design on DDR caching control with ping-pong operation for high-speed data acquisition system with PCI Express interface

摘要

Data caching is an indispensable part of high-speed data acquisition system, and it makes an important effect on coordinating the speed of data transfer and data processing. In the article, a data caching controller with ping-pong operation is designed after discussion on the features of data transmission with PCI Express interface. The controller's structure and principle is described, as well as the control logic. Additionally, the controller shows the idea of pipeline, where the command sending and data transfer control are separated on controlling the DDR controllers. The result indicates that the design could be widely used in the seamless caching and high-speed data process system. System efficiency will be improved, and the logic design will be simplified.