Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

摘要

In order to use Networks-on-Chip as communication infrastructure for heterogeneous, reconfigurable Systems-on-Chip, a set of tools are needed that would allow for an evaluation of the performance of a particular network, and a fast implementation of the system. In this paper we present two models that can be used in the design and implementation of the platform and of its applications. The first model is written in synthesisable VHDL, and it is highly parameterizable allowing a fast network implementation. The second one is a cycle-accurate SystemC model that allows a fast exploration of the design space. The models offer complementary information and help the platform and the application designers to make the best trade-offs. We present how the two models can be used for platform optimization and implementation and for application mapping, using a motion JPEG decoder as a case study. We analyze the system performance as a function of the different design parameters and we present the implementation results for the reconfigurable platform that we have built.