Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector

摘要

We present a Field Programmable Logic Devices (FPLDs) based implementation of a scalable filter architecture capable of detecting and removing impulsive noise in image sequences. The adaptive filter architecture is built using switching spatiotemporal filtering scheme and robust Lower-Upper-Middle (LUM) based noise detector. It uses highly optimized bit-serial pipelined implementation in Altera FPLDs. The proposed architecture provides real-time performance for 3-D image processing with sampling frequencies up to 97 Mpixels/second.