DVS

摘要

There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the designof modern digital systems. Verification engineers can simulatehardware in order to verify its performance and correctnesswith help of an HDL. However, simulation can'tkeep pace with the growth in size and complexity of circuitsand has become a bottleneck of the design process. DistributedHDL simulation on a cluster of workstations hasthe potential to provide a cost-effective solution to this problem.In this paper, we describe the design and implementationof DVS, an object-oriented framework for distributedVerilog simulation. Verilog is an HDL which sees wide industrialuse. DVS is an outgrowth of Clustered Time Warp,originally developed for logic simulation. The design of theframework emphasizes simplicity and extensibility and aimsto accommodate experiments involving partitioning and dynamicload balancing. Preliminary results obtained by simulatinga 16bit multiplier are presented.