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ADDITION WITH THREE PARALLEL CLA CIRCUITS

机译:三并联CLA电路的加法

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摘要

In this paper, a parallel version of the CLA addition algorithm will be introduced. In the presented algorithm three parallel CLA circuits are employed in the computation of the carries. The computations of the carries are equally divided among the three parallel CLA circuits. An octal, radix-8, logic is used in the parallel CLA algorithm. Despite the inclusion of the non-binary logic, the algorithm is completely realizable by binary gate. The parallel CLA algorithm and the traditional CLA algorithm are compared in terms of gate the delays.
机译:在本文中,将介绍CLA加法算法的并行版本。在提出的算法中,在进位的计算中采用了三个并行的CLA电路。进位的计算在三个并行CLA电路之间平均分配。并行CLA算法使用八进制基数8的逻辑。尽管包含了非二进制逻辑,该算法仍可以通过二进制门完全实现。在门延迟方面比较了并行CLA算法和传统CLA算法。

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