Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.
基于故障的边信道密码分析对对称和非对称加密算法非常有效。尽管可以使用简单的基于硬件和时间冗余的并发错误检测(CED)架构来阻止此类攻击,但它们会带来可观的开销(面积或性能)。在本文中,我们基于算法级别,循环级别和操作级别上加密和解密之间存在的反比关系,研究了针对对称加密算法的低成本,低延迟CED的系统方法,并开发了探索权衡的CED体系结构区域开销,性能损失和错误检测延迟之间的关系。所提出的技术已在AES决赛入128位对称加密算法的FPGA实现中得到验证。 P>
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