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Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

机译:2001年ASP-DAC 2001的诉讼程序。2001年亚洲和南太平洋设计自动化大会(猫。No.01ex455)

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The following topics were covered: device/circuit co-designing for advanced technologies; system level specification and simulation; BDD and sequential verification issues; interconnect design optimisation; design for manufacturability; system-level design; equivalence checking; parasitic extraction and reduced order models; functional decomposition and PLA-based logic synthesis; low power techniques for embedded software; asynchronous system design - architecture and low-power; analog design methodology; low power design methodology; advanced BIST; DSM design and analysis; signal integrity and analysis; design experiments for mobile applications; compilation techniques for embedded software; asynchronous system design - synthesis; system level power optimisation; multi-level logic optimization for logic circuits; practical and high level DFT; performance driven floorplaning and placement; delay and power estimation improvement; networked reconfiguration and systems; advances in timing optimisation of logic circuits; logic synthesis for low power and design space exploration; optimisation techniques for FPGAs; processor synthesis.
机译:涵盖以下主题:设备/电路共同设计用于先进技术;系统级规范和仿真; BDD和顺序验证问题;互连设计优化;可制造性设计;系统级设计;等价检查;寄生提取和减少订单模型;功能分解和基于PLA的逻辑合成;嵌入式软件的低功耗技术;异步系统设计 - 架构和低功耗;模拟设计方法;低功率设计方法;先进的BIST; DSM设计与分析;信号完整性和分析;移动应用的设计实验;嵌入式软件的编译技巧;异步系统设计 - 合成;系统级功率优化;逻辑电路的多级逻辑优化;实用和高水平的DFT;性能驱动的地板平面和放置;延迟和功率估计改进;网络重新配置和系统;逻辑电路定时优化的进步;低功耗和设计空间探索的逻辑合成; FPGA的优化技术;处理器合成。

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