In this paper, a model of superscalar processors using a network of Multiple-Class-Multiple-Pesource queues is de-scribed and studied. In this model, we are able to model and study instruction classes, instruction dependencies, the cache, the branch unit, the decoder unit, the central instruc-tion buffer, the functional units, the retirement buffer, the retirement unit and instruction issue policy in an integrated manner. This model has been verified against measured per-formance and has shown an average error of 5
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