There are two difficult issues in a formal treatment of high-level synthesis of dynamically reconfigurable systems: (1) Formulation of the time-varying mapping, (2)Reconfig-uration overhead optimization with design space explo-ration. In this paper, we present a graph-based algorith-mic framework to define and solve these problems. We use an extended control data flow graph (ECDFG) as in-termediate representations which abstract the temporal na-ture of a system in terms of the sensitization of paths in the dataflow. Based on this model, we propose a configura-tion bundling driven module allocation technique that can be used for component clustering ofr optimizing the recon-figuration overhead. Our graph-based algorithmic model allows the tasks of high-level synthesis to be specified as an optimization problem. Furthermore, we solve the optimiza-tion problem , Furthermore, we solve the optimiza-tion problem through a genetic algorithm, which performs temporal partitioning, module allocation and scheduling si-multaneousoy for maximizing resource usage and minimiz-ing reconfiguration overhead.
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