An Attempt to Completely Utilize the Bandwidth Capability of PCI-X 133MH_z Devices in a 66MH_z PCI-X Local Bus

摘要

In this paper I present a variation of the PCI-X 1.0 protocol which would prevent loss of valuable bandwidth in cases of transactions between two PCI-X-133 MH_z capable devices present in a local bus operationg at 66MH_z (due to the presence of atleast one PCI-X 66NH_z device on the bus). In conventional PCI-X protocol, there is no way by which transactions between two PCI-X 133MH_z devices can happen at 133MH_z when atleast one PCI-X 66MH_z device is also present on the bus. A variation of the PCI-X protocol presentd in this paper will eliminate the above limitation enabling high speed devices utilize their bandwidth capability to the maximum. The signalling scheme presented in this paper needs minimum changes to the PCI-X 1.0 version of the protocol and leads to bandwidth savings nearing 50