Automatic parllelism exploitation for FPL-based accelerators

摘要

The paper introduces the first complete programming framework for coarse grain dynamically reconfigurable accelerators and their application development.It includes a general model for cooperating host/accelerator platforms and a parallelizing compilation technique derived from it.The paper is an introduction illustrating these techniques and their principles by examples:a machine architecture (briefly),and its application development framework performing a "software-only" accelerator implementation (synthesis).The paper's focus is to explain the exploitation of four different levels of parallelism during this compilation process for achieving optimized speedups and hardware resource utilzation.