Increasing Memory bandwidth with wide buses: Compiler; hardware and performance trade-offs

摘要

Memory latency and lack of bandwidth are the main barriers to achieve high performace fro mcurrent and future processors. Specially in numeric applications. New organizations of the memory subsystem as well as hardware and software mechnaisms to effectitveyly exploit them are required. the apper presents a new cimpilation technique to pack several load/stores into a single wide load/store, so that the number of wide load/stores is maximized. It also evaluates the performance trade-offs of wide buses and the additional register pressure, showing that it is minimal nad has negligible effets. Finally, the paper proposes a hardware mechanism ot detect and group memory accesses into wide accesses at run time, aso that binary compatibility is peserved. the evaluations are performed using 1180 loops that represent about 78