Ispd2009 clock network synthesis contest

摘要

Clock network synthesis (CNS) is one of the most important design challenges in high performance synchronized VLSI designs. However, without appropriate problem examples and real-world objectives, research can become less relevant to industrial design flows. To address the need of the research community, we organize a clock network synthesis contest and a set of benchmark suite is released. Since the full-specification physical and electrical requirements of a leading-edge processor clock distribution would be cumbersome and impractical for this contest, we make the problem formulation familiar to the academia; that is to synthesize, buffer, and tune a clock distribution. However, the objective function has been modified to appropriately include the increasing importance of robustness to variation, in addition to the typical performance and power metrics. The paper briefly describes the ISPD clock network synthesis contest and the benchmark suite.