On stress aware active area sizing, gate sizing, and repeater insertion

摘要

Enormous technical and economic challenges facing technology scaling has rendered strain engineering techniques as the critical enabler of high performance designs in sub-$100$nm geometries. One of these techniques, source/drain (S/D) SiGe, has an interesting property that the mobility of the device is dependent on the size of active area (AA) surrounding it. To exploit this phenomenon for higher performance, a circuit designer needs first order and computationally tractable transistor level models. This paper provides the first AA sizing dependent RC switch level model of a logic gate which can be readily used by circuit designers. We derive the methodology to optimally use AA sizing for some common cells such as NAND, NOR and INV. For the first time, we formulate a convex optimization problem for concurrent AA and gate sizing problem for performance optimization and solve it optimally. We also analytically solve AA sizing aware optimal repeater insertion problem for dealing with the menace oflong global interconnects in modern chip design. Experimental results demonstrate that our methodology can reduce inter-chip long global interconnect delay by 9% and inter-module gate delays by 10% with only 11% increase in dynamic power dissipation.