This paper describes a tool implementing a Cellular Genetic Algorithm (CGA) [Balu93] for the solution of a combinatorial problem taken from the Electronic CAD area. Once an Integrated Circuit has been fully designed at the gate level, its layout must be drawn on the silicon surface, and the modules which compose it must be placed on the silicon area (Floorplan Design). A common practice is to first determine the relative positions of modules and then chose for each module the implementation which optimizes a given cost function.
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