We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. The method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. For cells with non-uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final(compacted) layout of the cell. We also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. The routing in the central region is completed by a new channel router at, or near, the channel density. The algorithms are implemented in a system call GENAC. The input to GENAC is a transistor net list, describing the connectivity as well as the size and type of each transistor. The output is a synthesized layout of the cell in symbolic language.
我们提出了一种解决细胞合成布局问题的方法,该方法可以实现多个优化目标。特别是,我们提出了一种新的分层方法,用于在单元中快速,最佳地放置晶体管。该方法使扩散中断的数量最小化,并且允许进一步追求次要优化目标,例如路由信道密度。对于具有不均匀的晶体管宽度的单元,以优化成本函数的方式折叠晶体管,该成本函数很好地近似于单元的最终(紧凑)布局的面积。我们还分析了单元生成问题中路由的特性,并设计了一种在晶体管上进行路由的算法。这样的路由降低了小区中心区域中的路由信道密度。中心区域中的路由是由一个新的通道路由器以等于或接近通道密度的方式完成的。算法在系统调用GENAC中实现。 GENAC的输入是一个晶体管网络列表,描述了连接性以及每个晶体管的大小和类型。输出是用符号语言显示的单元的综合布局。 P>
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