AWEsim: asymptotic waveform evaluation for timing analysis

摘要

Most timing analyzers rely upon a linear approximate interconnect model, typically an RC tree, to estimate efficiently the propagation delays for digital MOS integrated circuits. RC tree methods are adequate to analyze a large class of MOS circuits, but are not sufficient in general for high speed, dynamic and precharge MOS circuits. In addition bipolar logic and board level digital systems can have interconnect models which may not be compatible with RC tree topologies. In this paper we describe AWEsim, a variable refinement waveform estimator for generalized linear RLC approximate interconnect models.