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Performance analysis of speeded-up hgih-speed packet switches

机译:高速高速分组交换机的性能分析

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In this paper, we study the performance of high-speed packet switches, where the switch fabric operates at a slightly higher speed than the links, i.e. a speeded-up switch. As link speeds keep increasing, the speedup of N (number of links) needed for pure output queueing (which is the best) becomes a significant technical challenge. This is one of the main reasons for the renewed interest in moderately speeded-up switch fabrics. The aim of this paper is to highlight the result that only a moderate speed-up factor (less than two) is sufficient to achieve full input link utilization. In particular, we emphasize that this holds, even without relying on a central switch controller making intelligent decisions on which packets to schedule through the switch. As shown in recent works, i.e., (10, 12, 8, 2, 11), there are clearly benefits to using intelligent controllers, but they do come at a cost. Instead, in this paper we focus on what can be achieved by relying simply on switch speedup. We do so by means of analysis and simulations for average queue length in switches with speedup. We also present simulation results on delay performance.
机译:在本文中,我们研究了高速分组交换机的性能,其中交换矩阵的运行速度比链路(即加速交换机)的速度略高。随着链接速度的不断提高,纯输出排队(最好)所需的N(链接数)的加速成为一项重大的技术挑战。这是人们重新开始关注适度加速交换结构的主要原因之一。本文的目的是强调仅适度的加速因子(小于2)就足以实现完整的输入链路利用率的结果。尤其要强调的是,即使不依靠中央交换控制器来明智地决定要通过交换器调度哪些数据包,这一点仍然成立。如最近的作品(10、12、8、2、11)所示,使用智能控制器显然有好处,但确实要付出一定的代价。取而代之的是,在本文中,我们专注于仅依靠开关加速即可实现的目标。我们通过分析和模拟来加快交换机中平均队列长度。我们还介绍了有关延迟性能的仿真结果。

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