Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that can cross chip boundaries. This paper presents a large parallel architecture for generating moves in chess and shows how it can be restructured to reduce communication and permit a straightforward VLSI implementation without any performance loss. The result is a move generator comprising 64 identical custom chips performing at a rate of 500,000 moves per second, performance that is comparable to the best existing move generator.
The success of the architecture of a component module like a chess move generator depends not only on its performance but on how well it meshes with the rest of the system. We discuss the requirements of a chess move generator in the context of a chess-playing system and describe how each of these are met by our design. Details of the chip design are presented along with a description of how the move generator is built using identical chips.
使用VLSI技术实现大型并行电路时,通信是一个基本问题。必须使用宝贵的芯片面积来连接连接芯片上组件的导线,并且当前的封装技术限制了可跨越芯片边界的通信量。本文提出了一种大型并行架构,用于在国际象棋中生成动作,并展示了如何对其进行重组以减少通信并允许直接进行VLSI实现而不会造成任何性能损失。结果就是一个移动生成器,其中包含64个相同的自定义芯片,每秒执行500,000次移动,其性能可与现有最好的移动生成器相媲美。 P>
象棋移动发生器这样的组件模块架构的成功不仅取决于其性能,还取决于其与系统其余部分的啮合程度。我们在国际象棋游戏系统的背景下讨论了国际象棋棋盘生成器的需求,并描述了我们的设计如何满足这些需求。给出了芯片设计的详细信息,并描述了如何使用相同的芯片构建移动发生器。 P>
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