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Automatic verification of finite state concurrent system using temporal logic specifications

机译:使用时间逻辑规范自动验证有限状态并发系统

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We give an efficient procedure for verifying that a finite state concurrent system meets a specification expressed in a (propositional) branching-time temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global transition graph for the concurrent system. We also show how the logic and our algorithm can be modified to handle fairness. We argue that this technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite state concurrent systems.
机译:我们提供了一个有效的过程,用于验证有限状态并发系统是否满足(命题)分支时间时序逻辑中表示的规范。对于并发系统,我们的算法的复杂度在规范的大小和全局过渡图的大小上都是线性的。我们还展示了如何修改逻辑和算法以处理公平性。我们认为,该技术可以为手动证明构造或使用机械定理证明器提供实用的替代方法,以验证多个有限状态并发系统。

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