Automatic checking of logic design structures For compliance with testability ground rules

摘要

Specification of a set of design ground rules greatly simplifies the problems of testing and test generation for complex logic structures. This paper describes a fast and effective method for testing compliance of logic network designs to testability ground rules. The technique used is similar to logic simulation and may be performed as part of the design verification process. Very large designs may be checked quickly. The system provides an effective early warning tool for the logic designer and test engineer.