Enhancements of H.264 Encoder performance for video conferencing and videophone applications in TMS320C55X

摘要

In this age of multimedia convergence, video based applications for conferencing and streaming are seeing big market traction. The main challenge of implementing these systems is a tradeoff between several factors like bandwidth, image quality, implementation cost and speed (in terms of Mega Cycles per second). Moreover to implement this Encoder-Decoder system (CODECs) in a real time system based on any Digital Signal Processor (DSP) is more difficult because of their restricted resources like memory and CPU speed. In this paper, we present some novel approach, which reduces the computational complexity and also meets the memory constraint of the target processor for a standard H. 264 baseline encoder without sacrificing the rate-distortion performance. The proposed algorithms are applied on standard test sequence of different resolutions. The results obtained from a considerably large number of test sequences show the strength of our proposed algorithm. We claim the betterment in performance measured in Mega Cycles Per Second (MCPS) at the cost of negligible loss in image quality. Moreover we gain the betterment in image quality using algorithm modification in rate controlling. Implementation details are also presented for a QCIF H. 264 baseline encoder in a TMS320C55x DSP[8], which has only 256 KB RAM and 150 MHz clock speed. The enhanced performance is achieved thorough formulation of novel adaptive algorithms for rate control and motion estimation. We achieve almost 40% MCPS reduction at the cost of less than 1% reduction in image quality.