field programmable gate arrays; logic partitioning; iterative methods; simulated annealing; delay circuits; sequential circuits; logic CAD; force-directed placement algorithm; performance-driven placement algorithm; net-based placement algorithm; hierarchical FPGA; input netlist; net dependency graph; net-cluster level floorplan; simulated annealing; force-directed net placement; coarse net-level placement; force-directed logic cell placement; iterative computing; Munkres algorithm; force-directed method; Xilinx tools; post-layout delay; connection delay; MCNC combinational benchmark; MCNC sequential circuits;
机译:性能驱动的布局,可动态重新配置FPGA
机译:FPGA的基于力导向调度的架构生成算法和设计工具
机译:时序约束的FPGA布局:力导向的公式及其性能评估
机译:FPGA的力定向性能驱动放置算法
机译:性能驱动的FPGA同时布局和布线。
机译:FPGA中脉冲时序算法的仿真
机译:基于改进的力导向算法的性能驱动的标准单元布局器