Algorithm partitioning including optimized data-reuse for processor arrays

摘要

This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to processor arrays. Former design flows start with a space-time transformation, which we omit completely. Therefore, we are able to consider the constraints of target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized processor array for the 2D FIR filter algorithm.