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Configurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations

机译:在未来的MPEG-4电路实现中,用于标准DCT和形状自适应DCT的可配置VLSI体系结构

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Shape-adaptive block-based texture coding schemes such as the shape-adaptive DCT (SA-DCT) raise the need for an architecture performing efficiently the transform of variable length N. For an implementation with both standard DCT and SA-DCT required, it is advantageous to have a VLSI architecture which can be configured to compute both schemes. Existing fast algorithms usually consider only the standard DCT of fixed-size length and lack regular structure leading to complex routing. This paper discusses two different architectures satisfying the given requirement in terms of scalability, modularity and regularity. The first proposed architecture represents a time-recursive, fully modular but non-efficient structure regarding the number of operation counts. The second proposed feedforward architecture overcomes problems of numerical instability found in time-recursive structure. Both architectures are modeled in VHDL and synthesized using 0.7 /spl mu/m two metal-layer CMOS technology for comparison. The design in VHDL is kept generic so that new SA-DCT cores can be easily generated to produce application tailored circuits.
机译:诸如形状自适应DCT(SA-DCT)之类的基于形状自适应块的纹理编码方案提出了对有效执行可变长度N变换的体系结构的需求。对于同时需要标准DCT和SA-DCT的实现,具有可被配置为计算两种方案的VLSI架构是有利的。现有的快速算法通常仅考虑固定大小长度的标准DCT,并且缺乏规则的结构,从而导致复杂的路由。本文讨论了在给定的可伸缩性,模块化和规则性方面满足给定要求的两种不同体系结构。首先提出的体系结构代表了一种时间递归的,完全模块化但效率不高的结构,涉及到操作次数。第二种提出的前馈体系结构克服了时间递归结构中数值不稳定的问题。两种架构均以VHDL建模,并使用0.7 / spl mu / m的两种金属层CMOS技术进行合成以进行比较。 VHDL中的设计保持通用性,因此可以轻松生成新的SA-DCT内核,以生产应用定制的电路。

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