With the increasing recording densities, adaptive equalizers used in disk-drive read channels have to operate at high frequencies. Using traditional design techniques, a compromise has to be made between speed, power, latency and area of the chip. The proposed equalizer is based on an adaptive lattice filter with an improved stability and low-sensitivity to round-off noise due to the orthogonality between internal states. An increase of speed and a reduction of power consumption are achieved in the resulting structure by using high-speed and low-power multiplier architectures based on an improved partial product encoding and pipeline stages to reduce the length of critical paths.
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