The architecture of LabPET/spl trade/, a small animal APD-based digital PET scanner

摘要

The highly multiplexed, integrated analog processing front-end of current PET scanners yields high accuracy for timing and crystal identification, but also adds significant dead time and offers little flexibility for improvement. A new fully digital APD-based scanner architecture is proposed wherein nuclear pulses are sampled directly at the output of the charge sensitive preamplifier with one free-running ADC per channel. This approach offers the opportunity to explore new digital signal processing algorithms borrowed to command and control theory, as well as advanced heuristics such as neural networks. The analog front-end consists of a dedicated 0.18-/spl mu/m, 16-channel CMOS charge sensitive preamplifier. Digitization is performed with off-the-shelf dual 8-bit 45-MHz analog-to-digital converters. Digital processing is concentrated in a dual processor FPGA and a digital signal processor (DSP), which can process the data from up to 64 parallel channels with no dead time. The FPGA deals with the initial signal analysis for energy measurement and time stamping, while crystal identification is deferred to the DSP running computation-intensive auto-regressive algorithms. The entire system is controlled serially through a Firewire link by a graphic user interface. The initial LabPET/spl trade/ implementation of the system is a dedicated small animal scanner holding up to 3072 APD channels at an averaged count rate of up to 10 000 events/s each.