Design of a QPSK demodulator for DVB-S receiver ASIC chip

摘要

The paper presents the design of an all-digital QPSK demodulator, a key component of a satellite digital video broadcast receiver system and chip. The demodulator includes 3 sub-components: symbol synchronization loop; carrier frequency recovery loop; carrier phase recovery loop. The demodulator has a good performance at low SNR, a low system loss and reasonable complexity. The paper presents the design of the loops in detail, and gives the simulation results at optimum coefficients. The paper also shows the results of implementation in FPGA.