A fast, first level, R/spl phi/, hardware trigger for the D0 Central Fiber Tracker using field programmable gate arrays

摘要

We have developed an R/spl phi/ trigger using the eight doublet layers of axial fibers in the new Central Fiber Tracker for the D0 Upgrade Detector at Fermilab. This trigger must be formed in less than 500 nsec and distributed to other parts of the detector for a level trigger decision. The high speed is achieved by using massively parallel AND/OR logic instanced in state-or-the-art field programmable gate arrays, FPGAs. The programmability of the FPGAs allows corrections to the track roads for the as-built detector and for dynamically changing the transverse momentum threshold. To reduce the number of fake tracks at high luminosity the narrowest possible roads must be used which pushes the total number of roads into the thousands. Monte Carlo simulations of the track trigger have been run to develop the trigger algorithms and a vendor supplied simulator has been used to develop and test the FPGA programming.